1) Field of the Invention
The present invention relates to a technique for controlling a delay amount from when a signal is inputted to when the signal is outputted.
2) Description of the Related Art
In recent memory interface, the speed is increased year after year as seen in DDR3 (Double Data Rate 3) memory interface or the like standardized by JEDEC (Joint Electron Device Engineering Council).
When such memory interface is designed, DLL (Delay Locked Loop) is essential. Inside the DLL, used is a variable delay circuit being able to change the delay amount from when a signal is inputted to when the signal is outputted (refer to Patent Document 1 below, for example).
FIG. 14 is a diagram schematically showing one example of the configuration of a known variable delay circuit, illustrating a technique for changing the delay amount of a signal in a known variable delay circuit 90 formed of a plurality (ten in the example shown in FIG. 14) of delay elements 91-1 to 91-10 connected in series.
Incidentally, as reference character designating the delay element, reference characters 91-1 to 91-10 are used when it is necessary to specify one of the plural delay elements, whereas a reference character 91 is used when an arbitrary delay element is designated.
The known delay circuit 90 increases or decreases the number of the delay elements 91 through which a signal inputted from the forefront delay element 91-1 passes on the basis of a control signal inputted to a control signal input terminal of each of the delay elements 91-1 to 91-10, thereby to be able to change the delay amount from when the signal inputted to when the signal is outputted.
For example, when a High signal (refer to a reference character “H” in FIG. 14) is inputted as a control signal to a control signal input terminal CONT of the delay element 91-8 while Low signals (refer to a reference character “L” in FIG. 14) are inputted as control signals to control signal input terminals CONT of the delay elements 91-1 to 91-7 and 91-9 to 91-10 excepting the delay element 91-8, as shown in FIG. 14, a signal inputted from the forefront delay element 91-1 (refer to a reference character “IN” in FIG. 14) successively passes through a plurality of the delay elements 91-2 to 91-7 along a route from the delay element 91-2 to the delay element 91-7, turns back at the delay element 91-8, successively passes through the delay elements 91-2 to 91-7 in the inverse order along a route from the delay element 91-7 to the delay element 91-2, and is outputted from the forefront delay element 91-1 (refer to a reference character “OUT” in FIG. 14).
As above, in the known variable delay circuit, the delay amount of a signal from when the signal is inputted to when the signal is outputted is changed by increasing/decreasing the number of the delay elements through which the signal passes (propagates).
[Patent Document 1] Japanese Patent Application Laid-Open Publication No. 2005-286467